1. Technical Field
The present invention relates in general to data processing and, in particular, to the detection of hardware errors within a processor. Still more particularly, the present invention relates to a processor that self-tests for hardware errors in response to an instruction while operating in a normal mode.
2. Description of the Related Art
A typical superscalar processor comprises a digital integrated circuit including, for example, an instruction cache for storing instructions, one or more execution units for executing sequential instructions, a branch unit for executing branch instructions, instruction sequencing logic for routing instructions to the various execution units, and registers for storing operands and result data. In order to verify the proper operation of complex digital circuitry, such as the conventional superscalar processor described above, during normal functional operation, it is well-known to incorporate parity checking circuitry within the circuit design. However, because of the expense and complexity involved with parity checking each computational circuit of a superscalar processor, parity checking circuitry is often implemented only for storage circuitry, such as processor register files and on-chip cache memory. As a result, the computational circuitry of a conventional processor often remains untested during normal functional operation. Thus, computational errors resulting from a hardware failure may remain undetected, leading to corrupted data or system failure.
To address the above and other shortcomings in the art, the present invention provides a processor that utilizes no-op (or other predetermined) instruction cycles to perform a hardware test on processor circuitry without the need for complex parity checking circuitry.
In accordance with the present invention, a processor capable of self-test includes instruction sequencing logic, execution circuitry, data storage coupled to the execution circuitry, and test circuitry. The test circuitry detects for a hardware error in one of the instruction sequencing logic, execution circuitry, and data storage during normal functional operation of the processor in response to an instruction within an instruction stream provided by the instruction sequencing logic. In one embodiment, a hardware error can be detected by comparing values output in response to a test instruction by redundant circuitry that performs the same function. Alternatively or in addition, a hardware error can be detected by performing an arithmetic or logical operation having a known result (e.g., multiplication by 1, addition of 0, etc.) in response to the test instruction.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.